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90 clk osc lid base sealing terminal terminal plating rohs metal ceramic seam tungsten (metalized) gold / nickel (surface) / (under) compliant (pb-free) 57smo 7.0 0.2 5.0 0.2 1.2 0.26 1.14 1.14 1.4 1.4 1.4 2.54 5.08 2.54 2.6 1.2 1.7max. #3 #2 #1 #4 #5 #6 #3 #2 #1 #4 #5 #6 pin 1 connection "l" 2 n.c. 4z 3 gnd open or "h" output zc -output z : high impedance 6v dd 5 57smo 57smo low voltage positive emitter coupled logic oscillators 57smo (+2.5v or +3.3v fixed lvpecl models) standard smd clock oscillators item specifications standard specifications package item standard specifications package data package item 57smo t 1 40.000 mhz to 300.000 mhz 57smo(a) : ? 100 ppm 57smo(b) : ? 50 ppm 57smo(c) : ? 30 ppm 57smo(d) : ? 25 ppm 0?c to 70?c(standard) - 40?c to 85?c (w) 2.5v dc ? 5% 3.3v dc ? 5% v ih : 70%v dd min. v il : 30%v dd max. t 2 - 0.5v to 5.0v dc - 50?c to 125?c 90 ma max. 30 a max. 40% to 60% 45% to 55% 1 ns max. (20% to 80% of amplitude) v ol : 1.195v max. v ol : 1.745v max. v oh : 1.415v min. v oh : 2.215v min. 50
into v dd - 2v 200 ns max. 10 ms max. 10 ms max. 1 ps max. ? 5 ppm max. at 25?c ? 3?c for first year 250?c ? 10?c for 10 seconds 170?c ? 10?c for 1 to 2 minutes (preheating) lvpecl ( t 1) final exact part number to be determined with frequency, frequency stability, operating temperature and input voltage. e.g. 57smo(3.3vb)w 155.520 mhz. ( t 2) internal crystal oscillation to be halted (pin #1=v il ). generic part number frequency range frequency stability (0?c to 70?c) over all conditions operating conditions operating temperature input voltage (v dd ) stand-by control voltage (pin#1) absolute max. ratings supply voltage storage temperature input current (pin #1 = open or v ih ) stand - by current t 2 (pin #1 = v il ) output (0?c to 70?c) symmetry (at crossing point) rise and fall times "0" level "1" level load disable delay time enable delay time startup time rms jitter (12 khz to 20 mhz band) aging reflow condition vol voh tf tr t symmetry=t/t 100(%) t ermination : 50
impedance matching t 80% v pp 50% v pp 20% v pp v dd -2v v pp output waveform(1) vol voh tf tr t symmetry=t/t 100(%) t 80% v pp 50% v pp 20% v pp gnd v pp t ermination : high impedance probes output waveform(2) a #6 #5 output output #1 #2 gnd n.c. e/d sw tri- s tate #3 t.p. t.p. 50
50
#4 v dd1 v dd2 0.01 f 0.1 f 0.01 f 0.1 f v dd t ermination : 50
impedance matching v dd +3.3v +2.5v v dd 1 +2.0v +2.0v v dd 2 -1.3v -0.5v test circuit(1) a #6 #5 output output #1 #2 gnd n.c. e/d sw tri- s tate #3 t.p. t.p. r3 r4 r1 r2 #4 v dd 0.1 f v dd t ermination : high impedance probes note : r 3 & r 4 to change for the use of low impedance probes v dd +3.3v +2.5v r 1 130
270
r 2 130
270
r 3 82
62
r 4 82
62
test circuit(2) 2.54 2.54 5.08 1.6 1.6 1.6 0.94 0.94 1.6 1.6 2.2 0.01 f ? 0.1 f soldering pattern a 7.5 5.5 16.0 7.5 8.0 2.0 0.3 2.2 245 1000pcs qty/reel b c d f j l m reel dia. 4.0 0.1 2.0 0.1 1.75 0.1 + 0.1 - 0 1.5 l b f d a c j m t ape specifications actual size

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